Joel Emer's Publications

• Adaptive Insertion Policies for High Performance Caching,
  Moinuddin Qureshi, Aamer Jaleel, Yale Patt and Simon Steely, Joel Emer
  ISCA-34, San Diego, CA, June 2007.


• Late-Binding: Enabling Unordered Load-Store Queues,
  Simha Sethumadhavan, Franzi Roesner, Joel Emer, Doug Burger, Steve Keckler
  ISCA-34, June 2007.


• Computing the Architectural Vunerability Factor for Address-Based Structures,
  Arijit Biswas, Paul Racunas, Raz Cheveresan, Joel Emer, Shubhendu S. Mukherjee, and Ram Rangan,
  ISCA-32, June, 2005.


• The Soft Error Problem: an Architectural Perspective,
  Shubhendu S. Mukherjee, Joel Emer, and Steven K. Reinhardt,
  HPCA, Feb. 2005.


• Techniques to Reduce the Soft Errors Rate in a High-Performance Microprocessor,
  Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, and Steven K. Reinhardt,
  ISCA, Munich, Germany, June 2004.
  This paper was selected for the IEEE Micro 2004 issue on Top Picks of Computer Architecture papers.


• Cache Scrubbing in Microprocessors: Myth or Necessity?
  Shubhendu S. Mukherjee, Joel Emer, Tryggve Fossum, and Steven K. Reinhardt,
  10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), Papeete, French Polynesia, March 2004.


• A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor,
  Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steve Reinhardt, and Todd Austin,
  MICRO, Annaheim, California, December 2003.
  A version of this paper was selected for the IEEE Micro 2003 issue on Top Picks of Computer Architecture papers.


• A Comparative Study of Arbitration Algorithms for the Alpha 21364 Router Pipeline,
  Shubhendu S. Mukherjee, Federico Silla, Peter Bannon, Joel Emer, Steve Lang, David Webb,
  ASPLOS, San Jose, October 2002.


• Tarantula: A Vector Extension to the Alpha Architecture
  Roger Espasa, Federico Ardanaz, Joel Emer, Stephen Felix, Julio Gago, Roger Gramunt, Isaac Hernandez,
  Toni Juan, Geoff Lowney, Matthew Mattina, and Andre Seznec,
  ISCA-29, Anchorage, AK, June 2002.


• Asim: A Performance Model Framework,
  Joel Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee,
  Harish Patil, Steven Wallace, Nathan Binkert, Roger Espasa, and Toni Juan.
  IEEE Computer, February 2002.


• Loose Loops Sink Chips
  Eric Borch, Eric Tune, Srilatha Manne, Joel Emer,
  HPCA-8, Boston, MA, Feb. 2002.


• Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing,
  Harish Patil and Joel Emer.
  HPCA, Toulouse, France. January 2000.


• The Use of Multithreading for Exception Handling
  Craig B Zilles, Joel S Emer, Gurindar S Sohi,
  Micro-32, December 1999.


• Simultaneous Multithreading: Multiplying Alpha Performance,
  Joel Emer.
  Powerpoint presentation from Microprocessor Forum, October 1999.


• Memory Dependence Prediction using Store Sets,
  George Chrysos and Joel Emer,
  Published at ISCA25. June 1998.


• Simultaneous Multithreading: A Platform for Next Generation Processors
  Susan Eggers, Joel Emer, Hank Levy, Jack Lo, Rebecca Stamm, and Dean Tullsen.
  IEEE Micro, October 1997.


• Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading
  Jack Lo, Susan Eggers, Joel Emer, Henry Levy, Rebecca Stamm, and Dean Tullsen,
  ACM Transactions on Computer Systems, August 1997.


• A Language for Describing Predictors and its Application to Automatic Synthesis
  Joel Emer and Nick Gloy.
  ISCA, Chicago, IL, June 1997.


• Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multitheading Processor
  Dean Tullsen, Susan Eggers, Joel Emer, Hank Levy, Jack Lo and Rebecca Stamm.
  ISCA23, May 1996.
  Reprinted in "Readings in Computer Archictecture", 2000.


• Predictive Sequential Associative Cache
  Brad Calder, Dirk Grunwald, and Joel Emer,
  HPCA-2, February 1996.


• A System Level Perspective on Branch Architecture Performance
  Brad Calder, Dirk Grunwald, and Joel Emer,
  Micro-28, November 1995.


• Instruction Fetching: Coping with Code Bloat
  Rich Uhlig, David Nagle, Trever Mudge, Stuart Sechrest, and Joel Emer,
  ISCA-22, June 1995.


• Design and Implementation of the VAX Distributed File Service
  W.G. Nichols and J.S. Emer
  Digital Technical Journal, June 1989.


• Performance Analysis of Mass Storage Service Alternatives for Distributed Systems
  K.K. Ramakrishnan and J.S. Emer
  IEEE Transactions on Software Engineering, February 1989.


• Performance Considerations for Distributing Services - A Case Study: Mass Storage
  J.S. Emer and K.K. Ramakrishnan
  Proceedings of the 8th International Conference on Distributed Computing Systems, June 1988.


• A Model of File Server Performance for a Heterogeneous Distributed System
  K.K. Ramakrishnan and J.S. Emer
  Proceedings of the ACM SIGCOMM '86 Symposium, August 1986.


• A Programmable Interface Language for Heterogeneous Distributed Systems
  J.S. Emer and J.R. Falcone
  DEC Technical Report, DEC-TR-371, August 1985.


• Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement
  D.W. Clark and J.S. Emer
  Transactions on Computer Systems, February 1985.
  Reprinted in "Readings in Computer Archictecture", 2000.


• A Characterization of Processor Performance in the VAX-11/780
  J.S. Emer and D.W. Clark,
  Proceedings of the 11th International Conference on Computer Architecture, May 1984.
  Reprinted in "25 Years of the International Symposium on Computer Architecture", 1999
  Reprinted in "Readings in Computer Archictecture", 2000.


• Shared Resources for Multiple Instruction Stream Pipelined Processors,
  Joel Emer
  Ph.D. Thesis, R-838, Coordinated Science Lab, University of Illinois, July, 1979.


• Control Store Organization for Multiple Steam Pipelined Processors
  J.S. Emer and E.S. Davidson,
  Proceedings of the 1978 International Conference on Parallel Processing, August 1978.


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